The present invention relates to a technique of predicting yields of an electronic device such as a semiconductor integrated circuit at the time when an order for the product is received and at the time when the product is manufactured, and particularly to a technique of predicting yields of a semi-custom IC from which kinds of electronic devices can be produced by connecting circuit elements (macro-cells) depending on requests of customers.
Generally, a manufacturing process of an electronic device represented by a semiconductor integrated circuit can be broadly divided into a pre-process in which a plurality of chips are produced by stacking layers, such as circuit pattern layers, on a silicon wafer, and a post-process in which the silicon wafer is cut into individual chips to complete a product. Most defects generated in the course of manufacturing are generated in the pre-process. Accordingly, improvement in yield in the pre-process holds the key to electronic device business. Here, the yield in the pre-process means a rate of good chips determined by electrical inspection (probing test) as the final test in the pre-process. In other words, the yield in the pre-process means a ratio of the number of good chips to the number of all chips on a wafer.
Manufacturing of an electronic device whose circuit elements (macro-cells) are connected depending on requests of customers is small-volume production with large variety. Accordingly, to be sure of making a profit, it is necessary to predict yield of a product precisely and to decide a price properly at the time of receiving an order. In the case where it is found after the launch of a product that the yield is lower than the predicted value, then delivery to the customer is delayed since no substitute product exists. On the other hand, in the case where the yield is higher than the predicted value and surplus articles are produced, then those articles go to waste since there is a limited number of customers requiring the product. Thus, precise prediction of yield at the time of receiving an order of a product and at the time of manufacturing the product is essential to making a profit.
Failures as a cause of deterioration of yield of a pre-process can be broadly classified into functional failure and characteristic failure. A functional failure is a failure as a result of which a circuit does not operate normally, and arises mainly from breaking or shorting of a circuit pattern, which is caused in turn by a dust particle or a pattern defect occurring in the course of manufacturing. On the other hand, a characteristic failure is a defect as a result of which performance such as operating speed of a transistor or a capacitance of a condenser does not satisfy design specifications, and arises from slight variations in processing: for example, a variation in circuit dimension or oxide film thickness. Hereinafter in the present description, both dust particles and pattern defects, which become causes of functional failures, are referred to as a defect or defects.
As a simulation method for finding degree of functional failures caused by a defect, the Critical Area Analysis is a representative one. This is a method in which degree of occurrence of functional failures is calculated using a designed circuit pattern and a relation between the total number of defects generated and diameter of the defects. For example, PDF Solutions, Inc., USA, Defect and Yield Management (DYM), Inc., USA, and HPL, Inc., USA commercialize simulation software using the Critical Area Analysis.
Further, a yield prediction method using the Critical Area Analysis obtains an average fault ratio (probability that a defect creates a fault) by using a curve of POF (probability of failure) against defect diameter, which is made by inputting circuit pattern design layout data, and a curve of the normalized defect size distribution function, which is made by inputting results of inspection of the manufacturing line. The obtained average fault ratio is used to predict the yield (See Patent Document 1, for example).
Here, with respect to a relation between defect related yield Yr and defects, various yield models have been proposed and evaluated (See Non-patent Document 1, for example). According to the Poisson yield model, which assumes that defects occur uniformly at random positions in a wafer surface and their occurrence follows the Poisson distribution, the yield Yrb of a layer b is expressed by the following equationYrb=exp(−Dob*θb*S)  (Eq. 1)
In this equation, Dob is the total number of defects, which occur in a circuit layer b stacked in the pre-process) per unit area (total defect density), θb is an average fault ratio of the circuit layer b, and S is a chip area. It is difficult to know accurately the total defect density Dob of the defects occurring in the circuit layer b. Thus, in practice, the performance-based total defect density Dob′ is calculated using the actual yield Yrb′ of the circuit layer b, the average fault ratio θb and the chip area S. The calculated Dob′ is used to obtain a electric fault density (Dob′×θb) of the circuit layer b, and then the electric fault density is multiplied by the chip area S to calculate the defect related yield Yrb of the circuit layer b. Also, for each circuit layer (n) other than the circuit layer b, yield Yrn is calculated similarly. The yield of chips of the pre-process can be obtained by multiplying the yields of all the circuit layers (See Patent Document 1, for example).
On the other hand, the method by which the average fault ratio θ of chips is calculated by obtaining the sum of the respective average fault ratios of the circuit layers, and D0 is calculated from the actual yield Y and the chip area S according to the following equation Eq. 2 is disclosed (Patent Document 2, for example).ln(Y)=−D0*θ*S+ln(Ys)  (Eq. 2)Here, Ys is yield resulting from characteristic failures. In a yield maturity period in which slight variation in circuit dimension, oxide film thickness and the like, as causes of characteristic failures, is suppressed, the second term ln(Ys) of Eq. 2 becomes 0. As a result, when ln(Y) calculated from the yield of the yield maturity period and θ*S are plotted for various kinds of products, then a curve with gradient (−D0) is obtained. Here, D0 is an average value of the total number of defects that occur in a line. Using D0, an average electric fault density of a product whose yield is to be predicted is calculated, and a goal of the defect related yield can be calculated.
There is a method in which all the critical areas (each of which is obtained by multiplying an average fault ratio θ of the functional block in question by an occupied area S of that functional block) of functional blocks (such as an SRAM unit and a Logic unit) that can be arranged on a chip are obtained in advance, and an average fault ratio of the chip is calculated by dividing the sum of the respective critical areas of the functional blocks by the sum of the occupied areas (See Patent Document 3, for example).
Patent Document 1: Japanese Un-examined Patent Application Laid-Open No. 2002-76086
Patent Document 2: Japanese Un-examined Patent Application Laid-Open No. 2006-222118
Patent Document 3: Japanese Un-examined Patent Application Laid-Open No. 2004-31891
Non-patent Document 1: James A. Cunningham, “The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing”, IEEE Transactions on Semiconductor Manufacturing, Volume 3, Number 2, 1990
A gate array product is a semi-custom IC from which kinds of electronic devices can be produced by connecting circuit elements (macro-cells) depending on requests of customers. In a gate array product, logic gates are formed in a transistor formation layer and necessary gates only are connected through a wiring layer. By preparing in advance a wafer called a master that has been processed up to making a transistor formation layer, there is a merit in that a product satisfying a request of a customer can be manufactured and delivered in a short time. However, design layout data of the transistor formation layer have logic gates that are not ultimately connected. Accordingly, a result of calculation of an average fault ratio, using such design layout data as in the above-mentioned Critical Area Analysis, leads to a larger value than the average fault ratio of an actual product.
Further, a gate array product is characterized by factors such as a chip size, which determines an extent of the number of mountable logic gates, a logic part area ratio, i.e., a ratio of connected logic gates to chip area, SRAM occupancy, i.e., a ratio of mounted SRAM parts to chip area. There are many products in which these factors are different. Thus, it is difficult to calculate average fault ratios of all circuit layers in all kinds of gate array products.
When the method described in Patent Document 3 is applied to a gate array product, an average fault ratio is estimated by combining average critical areas of functional blocks mounted on a chip. Thus, it is not necessary to calculate an average fault ratio from design layout data. However, this method does not consider connection lines between the functional blocks, and it is difficult to forecast an average fault ratio considering effects of all the connection lines.
Further, also in the case of a cell-based IC in which previously prepared macro-cells are arranged and wired, random logic parts formed in the other areas than the arranged macro-cells are variously different depending on requests of customers. Thus, it is difficult to calculate respective average fault ratios of the random logic parts.
Further, the conventional method of predicting yield is a method using a total defect density Do calculated on the basis of an actual yield. The actual yield is measured with respect to products manufactured in the past. Accordingly, there is a time lag between the time when a wafer for which yield was measured flowed a production process of a circuit layer b and the time when a type of product whose yield is to be predicted flows in the production process of the circuit layer b. The total defect density Do has a decisive influence on the accuracy of yield prediction. Thus, although it is considered that the yield prediction of the conventional method is sufficiently accurate for pricing a product at the time of receiving an order for the product, the accuracy of the conventional prediction method is low for controlling input.
The present invention has been made considering the above conditions. An object of the present invention is to provide a technique that can accurately predict yield with respect to a semi-custom IC from which kinds of electronic devices are manufactured by connecting circuit elements (macro-cells) depending on requests of customers, for appropriate pricing at the time of receiving an order for a product and appropriate controlling of input in the course of manufacturing an electronic device.